The present invention relates to integrated circuit structures, and more specifically, to a method and structure that has different height field effect transistor structures.
As integrated circuit structures evolve, different shapes and surfaces are utilized to increase density. Within a transistor, the semiconductor (or channel region) is positioned between a conductive “source” region and a similarly conductive “drain” region, and when the semiconductor is in a conductive state, the semiconductor allows electrical current to flow between the source and drain. A “gate” is a conductive element that is electrically separated from the semiconductor by a “gate oxide” (which is an insulator) and (a field current/voltage) within the gate changes the conductivity of the channel region of the transistor.
Generally, transistor structures are formed by depositing or implanting impurities into a substrate to form at least one semiconductor channel region, bordered by shallow trench isolation regions below the top (upper) surface of the substrate. In this description, a “P-type transistor” is a positive-type transistor that uses impurities such as boron, aluminum, indium, gallium, etc., within an intrinsic semiconductor substrate (to create deficiencies of valence electrons) as a semiconductor channel region. Similarly, an “N-type transistor” is a negative-type transistor that uses impurities such as antimony, arsenic, phosphorous, etc., within an intrinsic semiconductor substrate (to create excessive valence electrons) as a semiconductor channel region.
One example of such advances is a transistor structure that has a three dimensional fin shape. The ends of the fin are usually conductive and can comprise, for example, source and drain regions of the transistor. The portion of the fin between the source and drain regions usually comprises a semiconductor and is covered by a gate oxide and gate conductor. This structure is sometimes referred to as a FinFET (fin-type field effect transistor). The gate conductor can form multiple gates on the different planar surfaces of the three-dimensional channel region of the fin and this structure is sometimes referred to as a MUGFET (multiple-gate field effect transistor).